1. Field of the Invention
The invention relates to an asynchronous nonvolatile semiconductor memory having an error correcting function, and a method of an access evaluation of the nonvolatile memory, specifically of evaluating a time delay caused by an error correction in order to assure the delay.
2. Description of the Related Art
The following Japanese patent documents disclose asynchronous nonvolatile semiconductor memories (hereinafter simply called “a nonvolatile memory”) having an ECC (Error Correcting Circuit), such as a Mask ROM (Read Only Memory), a PROM (Programmable Read Only Memory), an EPROM (Electrically Programmable Read Only Memory), an E2PROM (Electrically Erasable Programmable Read Only Memory), a FeRAM (Ferroelectric Random Access Memory) and a Flash memory.
Japanese patent Ref. No. H10-334696
Japanese patent Ref. No. 2005-347887
FIG. 11 shows a circuit diagram of an asynchronous nonvolatile memory 1 having an ECC in the related arts. The nonvolatile memory 1 includes a memory cell array 10 in which data are stored. The memory cell array 10 includes a plurality of word lines WL and a plurality of bit lines BL, each of which is perpendicular to the word lines WL. A memory cell 11 is formed at each intersection of the word lines WL and the bit lines BL, so that the memory cells 11 are disposed in a matrix. Each memory cell includes a transistor whose control gate is connected to one of the word lines WL, whose source is connected to one of the bit lines BL, and whose drain is connected to the power supply terminal via an unillustrated switching element. Such a transistor of the memory cell 11 further includes a floating gate. The memory cell in which electrons are injected onto its floating gate is recognized as the memory cell having data “1”. When electrons are not injected onto the floating gate in the memory cell, such a memory cell is recognized as the memory cell having data “0”.
The word lines WL are connected to a row address decoder 12, and the bit lines BL are connected to a column address decoder 13. The row address decoder 12 is a circuit for activating one of the word lines WL by selecting a desired row address from (A+1)-bit input addresses Ain [A:0](A=0, 1, 2, . . . A). The column address decoder 13 is a circuit for activating one of the bit lines BL by selecting a desired column address from the input addresses Ain [A:0], and is connected to a read amplifier circuit (hereinafter called “a read AMP”) 14.
The read AMP 14 amplifies a read-out signal outputted through the bit line BL controlled by the column address decoder 13 and outputs the amplified signal AMP_OUT [N:0] (N=0, 1, 2 . . . 127), and the output of the read AMP 14 is connected to a data latch circuit 15. The data latch circuit 15 latches the amplified signal AMP_OUT [N:0] and outputs the latched signal LATCH_OUT [N:0], and the output of the data latch circuit 15 is connected to an ECC 16. The ECC 16 as shown in the Japanese patent Ref. No. H10-334696 described above includes a plurality of exclusive OR gates (hereinafter called “an XOR gate”) and a plurality of AND gates. The ECC 16 receives the latched signal LATCH_OUT [N:0], and detects one-bit errors from data bits and a parity bit. When the ECC 16 does not find any errors, then it outputs an ECC output signal ECC_OUT [N:0] without delay from the time the latched signal LATCH_OUT [N:0] was inputted. After that, the memory 1 outputs the output data DATA_OUT [N:0] after a predetermined period during which the output data are transferred from the ECC 16 to the output terminal for external devices. When the ECC 16 finds a one-bit error, it corrects the one-bit error by an arithmetic operation for correction and outputs the corrected output data DATA_OUT [N:0].
FIG. 12 is a timing chart showing a read-out operation of the nonvolatile memory 1 in the case that the there is no defects in a selected memory cell 11.
In the read-out operation of the nonvolatile memory 1 having no defects in its memory cells, the input address Ain [A:0] is applied to the row address decoder 12 and the column address decoder 13 at the time t1, then a single memory cell 11 is selected by the row address decoder 12 and the column address decoder 13. An electric current flowing from the selected memory cell 11 is amplified for an expectation-determination by the read AMP 14 at the time t2. The amplified signal AMP_OUT [N:0] showing the expectation as a result of the determination is latched in the data latch circuit 15 at the time t3. Since the amplified signal AMP_OUT [N:0] is latched in the data latch circuit 15 once, the stable signal that is the latched signal LATCH_OUT [N:0] is inputted to the ECC 16. If there are no expectation error in the latched signal LATCH_OUT [N:0], no arithmetic operation for correction is performed. Thus, no delay occurs between the time when the latched signal LATCH_OUT [N:0] is inputted to the ECC 16 and the time when the output data DATA_OUT[N:0] is outputted. Thus, the memory 1 outputs the output data DATA_OUT [N:0] at the time t4 after a predetermined period during which the output data are transferred from the ECC 16 to the output terminal for external devices.
FIG. 13 is a timing chart showing the read-out operation of the nonvolatile memory 1 in the case that the there is a defect in a selected memory cell 11.
In the read-out operation of the nonvolatile memory 1 having the defect in its memory cell, when there is an expectation bit failure in the latched signal LATCH_OUT [N:0], the arithmetic operation for correction is performed in the ECC 16. Thus, while the latched signal LATCH_OUT [N:0] is inputted at the time t3, the ECC 16 outputs the ECC corrected output signal ECC_OUT [N:0] at the time t4 because of the process time of the arithmetic operation for correction. Thus, a time delay occurs between the time when the latched signal LATCH_OUT [N:0] is inputted to the ECC 16 and the time when the output data DATA_OUT[N:0]. For this reason, the memory 1 outputs the output data DATA_OUT [N:0] at the time t5 after a predetermined period during which the output data are transferred from the ECC 16 to the output terminal for the external devices because of the time delay caused by the ECC 16.
As explained above, the output data DATA_OUT [N:0] is outputted at the time t4 when the selected memory cell has no defects while it is outputted at the time t5 when the selected memory cell has a defect. Since the time of the output is different in accordance with the existence of the defect, it is required to perform the access evaluation including the delay caused by the ECC's arithmetic operation for correction before sipping shipping the nonvolatile memory 1 from a manufacture to customers. In other words, the read-out data from each memory cell of the nonvolatile memory 1 should be evaluated at the access timing that includes the delay for the arithmetic operation for correction is included, that is, at the time t5.
This is because of the following reason. As described above, the data “1” or “0” are stored on the floating gate of each memory cell 11, depending on the condition that the electrons are injected thereon. After the shipment of the nonvolatile memory 1 having data in its memory cell 11, the electrons in a certain memory cell 11 are sometimes erased by an accident, such as a retention characteristic change of memory cells. If it happens, the memory data is changed. It is unpredictable in which memory cell the retention characteristic change occurs. In other words, this phenomenon may occur in any of the memory cells 11. For the manufacture, it is necessary to consider that the memory data is changed after the shipment in order to maintain the product liability. Thus, before the shipment of the nonvolatile memory 1, the read-out data should be evaluated by setting the nonvolatile memory 1 in the condition that its memory data is changed (that is the condition that the defect is found in the memory cell). Accordingly, the ECC 16 delays the timing of its output under the condition that the defect exists in a certain memory cell because of the arithmetic operation for correction.
However, any nonvolatile memory 1 having a defect cell is removed from the production line in an advance memory test by a manufacturer. Thus, no memory cells having an expected error are included in the nonvolatile memory 1 for shipping. Thus, the access evaluations are only performed at the timings t1-t4 illustrated in FIG. 12. Furthermore, the access evaluations cannot be performed at the timings t1-t5 illustrated in FIG. 13 for all variations of the expected error in the memory cell.